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| Advanced Power Electronics Corp. 2A Sink/Source Bus Termination Regulator Description The AP1250CMP is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices requirements. The regulator is capable of actively sinking or sourcing up to 2A while regulating an output voltage to within 40mV. The output termination voltage cab be tightly regulated to track 1/2VDDQ by two external voltage divider resistors or the desired output voltage can be pro-grammed by externally forcing the REFEN pin voltage. The AP1250CMP also incorporates a high-speed differential amplifier to provide ultra-fast response in line/load transient. Other features include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection. The AP1250CMP are available in the ESOP-8 (Exposed Pad) surface mount packages. AP1250CMP Features Ideal for DDR-I, DDR-II and DDR-III VTT Applications Sink and Source 2A Continuous Current Integrated Power MOSFETs Generates Termination Voltage for SSTL_2, SSTL _18, HSTL, SCSI-2 and SCSI-3 Interfaces. High Accuracy Output Voltage at Full-Load Output Adjustment by Two External Resistors Low External Component Count Shutdown for Suspend to RAM (STR) Functionality with High-Impedance Output Current Limiting Protection On-Chip Thermal Protection Available in ESOP-8 (Exposed Pad) Packages VIN and VCNTL No Power Sequence Issue RoHS Compliant and 100% Lead (Pb)-Free Application Desktop PCs, Notebooks, and Workstations Graphics Card Memory Termination Set Top Boxes, Digital TVs, Printers Embedded Systems Active Termination Buses DDR-I, DDR-II and DDR-III Memory Systems Pin Configuration ESOP-8 (MP) (Top View) VIN GND REFEN VOUT Block Diagram NC NC VCNTL NC 1 8 2 7 GND 3 6 4 5 Pin Description Pin Name VIN GND VCNTL REFEN VOUT Power Input Ground Gate Drive Voltage Reference Voltage input and Chip Enable Output Voltage Pin function 1 200901074 AP1250CMP Absolute Maximum Rating (1) Parameter Input Voltage Control Voltage Power Dissipation Storage Temperature Range Lead Temperature (Soldering, 5 sec.) Package Thermal Resistance Symbol VIN VCNTL PD TS TLEAD JC Value 6 6 Advanced Power Electronics Corp. Unit V V -C C C/W Internally Limited -65 to 150 260 28 Operating Rating(2) Parameter Input Voltage Control Voltage Ambient Temperature Junction Temperature Symbol VIN VCNTL TA TJ Value 2.5 to 1.5 3% 5.5 or 3.3 5% -40 to +85 -40 to +125 Units V V Electrical Characteristics VIN=2.5V/1.8V/1.5V, VCNTL=3.3V, VREFEN=1.25V/0.9V/0.75V, COUT=10F (Ceramic)), TA=25C, unless otherwise specified Parameter Input VCNTL Operation Current Standby Current Output (DDR / DDR II / DDR III) Output Offset Voltage(3) Load Regulation (4) Symbol Test Conditions Min Typ Max Units ICNTL ISTBY VOS VLOAD IOUT=0A VREFEN < 0.2V (Shutdown),RLOAD = 180 ---20 -20 1 50 --- 2.5 90 +20 +20 mA A mV IOUT= 0A IOUT= +2A IOUT= -2A Protection Current limit Thermal Shutdown Temperature Thermal Shutdown Hysteresis REFEN Shutdown Shutdown Threshold ILIM TSD TSD VIH VIL 3.3V VCNTL 5V 3.3V VCNTL 5V 2.2 125 -0.6 -- -170 35 --- ----0.2 A Enable Shutdown V Note 1: Exceeding the absolute maximum rating may damage the device. Note 2: VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN Note 3: VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN. Note 4: Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load regulation in the load range from 0A to 2A. 2 Advanced Power Electronics Corp. Application Information Input Capacitor and Layout Consideration Place the input bypass capacitor as close as possible to the AP1250CMP. A low ESR capacitor larger than 470uF is recommended for the input capacitor. Use short and wide traces to minimize parasitic resistance and inductance. Inappropriate layout may result in large parasitic inductance converter. and cause undesired oscillation between AP1250CMP and the preceding power Thermal Consideration AP1250CMP AP1250CMP regulators have internal thermal limiting circuitry designed to protect the device during overload conditions.For continued operation, do not exceed maximum operation junction temperature 125. The power dissipation definition in device is: PD = (VIN - VOUT) x IOUT + VIN x IQ The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula: PD(MAX) = ( TJ(MAX) -TA ) /JA Where TJ(MAX) is the maximum operation junction temperature 125, TA is the ambient temperature and the JA is the junction to ambient thermal resistance. The junction to ambient thermal resistance (JA is layout dependent) for ESOP-8 package (Exposed Pad) is 75/W on standard JEDEC 51-7 (4 layers, 2S2P) thermal test board. The maximum power dissipation at TA = 25 can be calculated by following formula: PD(MAX) = (125 - 25) / 75/W = 1.33W The thermal resistanceJA of ESOP-8 (Exposed Pad) is determined by the package design and the PCB design. However, the package design has been decided. If possible, it's useful to increase thermal performance by the PCB design. The thermal resistance can be decreased by adding copper under the expose pad of ESOP-8 package. We have to consider the copper couldn't stretch infinitely and avoid the tin overflow. Consideration while designs the resistance of voltage divider Make sure the sinking current capability of pull-down NMOS if the lower resistance was chosen so that the voltage on VREFEN is below 0.2V. In addition, the capacitor and voltage divider form the lowpass filter. There are two reasons doing this design; one is for output voltage soft-start while another is for noise immunity. 3 AP1250CMP Advanced Power Electronics Corp. Application Diagram R1 = R2 = 100K, RTT = 50/33/25 COUT, min = 10F (Ceramic) + 1000F under the worst case testing condition CSS = 1F, CIN = 470F(Low ESR), CCNTL = 47F 4 ADVANCED POWER ELECTRONICS CORP. Package Outline : ESOP-8 NOTES:Thermal Pad Dimemsions 2.25 0.1 Millimeters SYMBOLS MIN NOM MAX A 8 7 6 5 A 5.80 4.80 3.80 0 0.40 0.19 0.00 0.35 1.35 6.00 4.90 3.90 4 0.65 0.22 0.08 0.42 1.55 0.375 REF. 45 1.27 TYP. 6.20 5.00 4.00 8 0.90 0.25 0.15 0.49 1.75 B C C D E F 1 2 3 4 M H L G H B J K G A2 L I J 1.All Dimension Are In Millimeters. 2.Dimension Does Not Include Mold Protrusions. Part Marking Information & Packing : ESOP-8 Part Number Package Code 1250CMP YWWSSS Date Code (YWWSSS) YLast Digit Of The Year WWWeek SSSSequence 5 |
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